• Cortex A15 SCU
    Hi, I find no introduction about SCU registers of A15 in the TRM. So, can software control SCU? Especially is SCU needed to be enabled by software? Thanks&Regards.
  • Exception / Interrupt for Cortex-A15
    Hi, I would like to know whether my understanding is right or not regarding to the interrupt (exception). When an interrupt is issued, the interrupt is executed at once without the completeion of the...
  • Type 2 Hypervisor with Hardware Assisted Virtualization as Cortex A15
    Respected Experts,                               I would like to know that is it possible to get the advantage of Hardware Asssited Virtualization to develop a Type 2 Hypervisor which runs on an OS, and...
  • Cortex-A15 MPCore: How to Enable Monitor Debug Mode
    Hi experts, I want to enable monitor debug mode for Cortex-A15 MPCore. I tried modifying DSCR[15] bit but watchpoint event still won't generate exception/abort. Core was in no-debug mode before modifying...
  • Cortex-A8/A15 L1 cache
    Hi, I would like to know whether the cortex-A8/A15 L1cache has ECC or parity check for error checking, or not. I know L2 cache has ECC function. Bur I don't know about L1 cache. Please let me know. Best...