• Cortex-A9 PMU cycle counter not always incrementing at CPU frequency?
    Hello, I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU...
  • What is real application of Exclusive access in AXI
    Hi,   What is real time application of AXI exclusive access.   Is it necessarily to do Exclusive read first then exclusive write.   May i know the reason is it so?
  • AMBA3 AXI - Exclusive access
    1/ What will happen when a master performs 2 exclusive read with 2 different transaction ID to the sam an address location?? Example: Master0 (M0) issue 2 exclusive read with 2 different transaction ID...
  • Does load/store-exclusive violate Hypervisor Transparency?
    Hello Community, I am currently learning hypervisor design using ARM's virtualization extensions (on both ARMv7 and ARMv8). A note in the ARMv8-A reference manual (section D1.5) mentions: "In some systems...
  • What are hints?
    What does it mean that an instruction is a hint instruction, like NOP, YIELD and WFE? I haven't found any explanations in ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, Issue C. ...