• Problems with  AXI4  write data channel
    Hello:     Suppose there are 2 masters(master0 and master1) and 2 slaves(slave0 and slave1) for AXI4. As AXI4 protocol has removed WID signal for write data channel, When slave0 has received wvaild which...
  • Reason for having decouple write address, data channels in AXI4
    Can someone explain me the advantage of having decouple write address, data channels in AXI4? In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of...
  • Write interleaving with Multi-AXI master
    Hi, I have multiple questions related to multi-master AXI4 system. Eg: lets say we have 2 masters(m1,m2) and 2 slaves(s1,s2) and an interconnect. 1) In parallel, Can i have transfers(burst) to m1->s1...
  • AXI Write data interleaving
    Hello Everyone, [ This not specific to AXI3/4 ] Can someone give an example on how write data interleaving works? Is it used only when we have multi-master cases? or its possible with single-master cases...
  • can we delay read and write transactions(axi4) by providing delay in register slice?
    Basically I want to provide delay of 15 clock cycles  for writing and reading through axi4 bus .Is it possible?