• Question about PMU in detail
    Hi everyone~ My questions focus on PMU for armv8. In architecture reference manual Armv8 I can always find words like "If xxx is implemented", in which, xxx may be armv8.6-ecv/ armv8.5-PMU/PMUv3.1 etc...
  • ARM PMU access DRAM Event
    Hi, accorting to the reference manual of cortex A7 https://static.docs.arm.com/ddi0464/f/DDI0464.pdf pagina 243, what event number i neet to select to count all the DRAM access (read / write)?
  • How to configure Cortex-A57 PMU
    I asked this question in a different community space but it seemed like this is a more appropriate home. I'm trying to configure the performance counters for the Cortex-A57 and I'm very confused. The...
  • ARMv8 PMU access
    Hey guys, I'm running a sw in a multicore ARMv8 system and I'd like to know a bit more about the PMU component. There is a PMU per CPU, right? Is it possible from one CPU to access the other CPU...
  • What does PMCEID0_EL0 determine for the the PMU? Performance monitor config
    The TRM for the a-57 states that PMCEID0_EL0: Defines which common architectural and common micro-architectural feature events are implemented. PMCEID1_EL0 is a continuation of this list. If a bit position...