• Address handshaking in AXI4
    Hi  there, I have question regarding handshaking in the AXI protocol.Currently i am designing  decorder for AXI4-Lite master . While doing the write adress  transaction, AWVALID  depends upon write enable...
  • AXI4 VIP unable to change values of control signal
    I'm using AXI VIP example design in Vivado 2020.1, Can anyone here explain how can I setup AWVALID, AWREADY, ARVALID, ARREADY. My design is: AXI VIP master --> AXI Interconnect --> 4 BRAM controller...
  • Are there any restrictions for the width of an address signal in an AXI4 interface?
    Hello, in the AXI4 specification I didn't find anything mentioned about width restrictions for the address signal. I'm currently trying to simulate a component which I wrote in VHDL which provides an...
  • Address decoding in AXI4 interconnect
    Hi, anybody explain how data  is routed in interconnect? As stated in AXI4 spec, only start address issued from master,then how it is done in case of burst transaction? Please Explain how this is done...
  • AXI4: Unaligned read transactions
    Hi guys, I'm new to the AXI ecosystem. However, I have one question related to unaligned read transfers. Does AXI4 support unaligned read transfers although er are no strobe lines? If so, which data on...