• What's the difference between LDAXR and LDREX
    Hi experts: In armv8 specification, I have found two types of exclusive access instructions: LDAXR/STLXR and LDREX/STREX. I have some questions about these instructions: (1) What's the difference...
  • Cache Coherence
    Hi ,    I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid.    1. Bring Core 1 out of reset.    2. Bring Core 2 out of reset.    3. Invalidate...
  • Cache coherency in big.little system.
    Within an arm system, a cluster is an ACE master connected to the Arm CCI. To keep the cache coherency, the cluster would send some transactions to the bus and are trapped by the snoop filter of CCI....
  • How to flush write buffer when memory attribute is normal_nc
    Hi, I am working on access pcie bar in armv8-a cpu(cortex-A5x) powered soc. Right now, I encounter an issue about (maybe) coherent issue. When I write data(4 bytes aligned) to pcie bar with ioremap_wc...
  • What is the difference between ARM cortex-A and cores in snapdragon from Qualcomm?
    Hi All, What is the difference between ARM cortex-A and cores in snapdragon from Qualcomm? I know that they say it is compatible with ARMv7/8 ISA. Regards Nitin