• ARMv8-A: Is an ISB instruction required after writing to the CPSR register in AARCH32 state?
    For example, write cpsr as following code snippets: mov r1, sp movw lr, #0x393 movt lr, #0 msr cpsr_cxsf, lr do_irq: ... Is an ISB instruction required after " msr cpsr_cxsf, lr "? Thank...
  • MRS/MSR (Banked register)
    What can be accessed by MRS/MSR in user mode? In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1): B9.3.10      MSR (Banked register) cond  0 0 0 1 0 R 0 0        M1      Rd  (0) (0) 1 M 0 0 0 0 (0...
  • Where can I find "ARMv8 Instruction Set Overview" (PRD03-GENC-010197)
    I am trying to prepare a guide for people that want to start programming in A64 assembly and I think the document would be a nice resource. It is mentioned in multiple places like here on developer.arm...
  • AArch64 TLB maintenance requirements
    Hello all, I want to improve VM operation in AArch64 port of FreeBSD but I stuck on following problem. The FreeBSD VM subsystem is capable to map various *kernel* objects by using superpage (higher order...
  • why some instructions are not required to be  explicitly synchronized ?
    Dear all: In "ARM® Architecture Reference Manual ARMv8", B2.6.5 Concurrent modification and execution of instructions , it says some instructions, such as " B, BL, NOP, BRK, SVC, HVC, and SMC " dont need...