• how pc is updated during execution of SWI and any simple instruction like mov R1,R15?
    when swi instruction is executed at that time it is said that pc is not updated yet so it is pointing to instruction next to swi instruction for example addr code 0x0000 swi 100 0x0004 mov r1,r2 0x0008...
  • Return address from FIQ_Handler. Do we come back to the next instruction?
    Is it MOVS pc, r14 or SUBS pc, r14, #4 This is written in the ARMDEN0013D. but in the table it says next instruction whereas the SUBS pc, r14, #4 means the instruction which was interrupted.
  • Modify SP register and PC register in Cortex-M1 using Keil
    Hi, I'm planning to do a bootloader for a Cortex-M1 processor but i'm having serious problems. First of all, the Keil says it expect a ")" when writing this type of inline assembly: __asm__ __volatile__...
  • Safe exit from HARD FAULT on CortexM0
    Hi All, I am developing on a CM0+ with functional safety support. The safety manual requires to test some features before activating safety functions; many of these are straightforward while others...
  • ARM Cortex-A9 MPCore check stack usage
    Hi experts, I want to check the actual usage of my program on Xilinx SDK 2015.4. I connected to ARM Cortex-A9 MPCore#0 using the connect command in XMD console as shown below: When I used stackcheck...