• Cache Memory Requirement
    Hi Experts, How to derive the cache memory requirement for the working of the software ? I could understand that each of the A/M/R processors have its own applications and build with its own Cache size...
  • cache invalidation
    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...
  • Cache ECC in Cortex-R5 & Event bus
    Hi everybody, I am using a Cortex-R5 embedded in a TMS570LC4357, and I am wondering to use the cache configuration as "Do not generate Aborts, force write through, enable hardware recovery". As far...
  • ARM1136: why the mismatch between cache stalls and cache misses ??
    Something weird when I count both Instruction Cache Miss event and event 0x1 (viz. “Stall because instruction buffer cannot deliver an instruction. This could indicate an Instruction Cache miss or an...
  • When the data CPU wants to access is not in the cache the related block will always be copy to the cache, is this right?
    When the data CPU wants to access is not in the cache the related block will always be copy to the cache, is this right? In the above question, the related region refers to the region seted to be cachealbe...