• Cortex-A8 : instruction fetch for dual-issue
    Hi, We experiment the following loop code (runs 4096 iterations) and we get CPI=0.66 (in other words, loop initiation interval (II) is about 6 machine cycles). We are trying really hard  to reason why...
  • is it possible to flush/invalidate cache from user space for AARCH32
    Hi, When AARCH64 works at AARCH32 mode, is it possible to flush/invalidate cache from user space? i know AARCH64 can do that, but is it capable for AARCH32? i am working on a user space driver and i need...
  • Getting ERROR "unknown mnemonics for UQSUB8 instruction"
    Hi community, I have tried to compile the source code for openVG I have given proper cross compiler which is required by the platform still I am getting the error of unknown mnemonics for the instruction...
  • How many cycles requires the instruction QBNE?
    QBNE (Quick branch not equal) Using the PRU in the Beaglebone black (AM335x 1GHz ARM® Cortex-A8) I am asking how many cycles requires the instruction QBNE? qbeq myLabel, r1, 0 I suppose two if the comparison...
  • Code for integer division on Cortex-A8?
    Hi all, when I wrote a C code with division operation the compiler is generating some library calls.....when I tried to see the equivalent code for those function calls...I'm unable to reach there (may...