• What happens to the Instructions already in pipeline when interrupt occurs ?
    Hello Community, Recently I was going through some code and has this doubt. My Pseudocode ============ CPSID I - Disable interrupts Do critical work CPSIE I - Enable interrupts Do non critical...
  • hello , How to enable / disable a global interrupt on cortex M7
    hello , How to enable / disable a global interrupt on cortex M7 youssef
  • A8: Keeping Cache-enabled and MMU-disabled
    Hi all, A Question about the A8 processor. If I enable the L1 and L2 caches, I see a performance boost even if the MMU is disabled. I was under the impression that the MMU is required to be enabled...
  • ARM Cortex A8 - if IRQ interrupts are disabled in CPSR register While the processor is executing, system results in data abort. What might be the reason to trigger data abort
    ARM Cortex A8 - if IRQ interrupts are disabled in CPSR register While the processor is executing, system results in data abort. What might be the reason to trigger data abort cpsid i;          // instruction...
  • Minimal Frequency of Operation
    Hello, Is there any data regarding the minimum and maximum frequency a processor can operate in ARM V-7 ?