• what is VIPT behaves as PIPT?
    1. I READ the cortex-a78 trm, i confuse with the L1 Cache, what is VIPT behaves as PIPT? if L1 Cache is VIPT, Can it be understood as On a memory access operation, core get the physical addresses from...
  • Why A15 I-cache use PIPT while other series use VIPT
    Hi Expert, I know that VIPT have some alias problem, but it save more power than PIPT. As a trade off, many A-series use VIPT on their I-Cache, due to the i-cache is read only. So, I'm confused...
  • cache invalidation
    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...
  • L2 cache with cortex-A8
    Hello, Can I assume that with cortex A8 cache invalidate/flush is used only with L1 ? I have some 2 implementation of this routines, one is called L1 and the other L2C-310. I am just not sure if using...
  • Cache maintanance operation to PoC
    Hi experts, I'm quite confused about cache maintanance operation to PoC on Cortex-A9 (with PL310 L2 cache controller). I'm refererring to the following operations: - DCIMVAC, invalidate data cache by...