• AXI4: Wider transactions than BUS width allowed?
    Hi AXI-experts, Does AX4 support burst sizes larger than the bus width? Narrow transactions are allowed, but do wider transactions also work? Best regards, Robert
  • L1 data cache and unified cache disabled in AMP mode for Cortex-a7
    Hello Guys, in my system ( multi core cortex- a7 ), I do not want to be in SMP mode that means it is AMP mode and i need to clear the ACTLR.SMP bit to be in AMP mode but the strange thing which i found...
  • Cortex-A7 cache line size
    Hi All, when I read the ARM® Cortex -A Series Programmer’s Guide for ARMv7-A I found that at page 8-12 Tabel 8-1 Cache features of Cortex-A series processors (continued) there is a field say that...
  • How get ARMv7 cache size
    Hi everybody!! I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15). In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the...
  • Extended System Coherency: Part 1 - Cache Coherency Fundamentals
    Chinese Version 中文版: 扩展系统一致性 - 第 1 部分 - 缓存一致性基本信息 Introduction The theme of TechCon 2013 was “Where intelligence connects” and in many ways hardware system coherency is an important part of connecting...