• In AXI Interface, is the VALID signal of the master dependent on the slave's READY signal
    Hi, I am seeing an issue, where the READY signal's assertion depends on the VALID signal. If the VALID signal remains asserted through out the transaction (Say, for a burst transfer), then for the second...
  • Cortex-A9-PL310 AXI connection
    Hi experts, I would like to know more about the interconnection between Cortex-A9 and the PL310 L2 cache controller. I think Figure 1.2 in the TRM is a good starting point: CoreLink Level 2 Cache Controller...
  • AXI problem
    Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...
  • How should a AXI MASTER or SLAVE behave when a xREADY signal is never asserted?
    Hi all, I was trying to extract this information from the AXI specification but I didn't find any clear answer. I wonder how should an AXI component behave if an input xREADY signal is never asserted...
  • AXI narrow transfers
    I would appreciate assistance on the following: Suppose a bus master with 128bit data width. This master access a 64bit slave via AXI matrix as follows: awaddr = 0x4000_909F awsize = 0x0 (8bit write)...