• Inconsistent shareability domain on tlbi instructions
    I'm using a IMX8QM system which features a dual-core A72 cluster plus a quad-core A53 cluster. Running on EL2 from one of the A53 cores I want to unmap a single page for all cores, so after I remove the...
  • Cortex A53 : Cache policy setting
    Hi, Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? I'm enabling the caching using the SCTRL register...
  • ARMv7 CortexA9 Cache Policy - No allocate ?
    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A...
  • shareability attribute for armv8 cortex a-53
    Hi, I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512. My question is how...
  • shareable attribute in armv8
    Hi Experts,                     I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different. I could see how to set the different page attributes like...