• Permission fault, level 2 on MMU enable
    Hi ARM folks, hoping someone can show me where I'm going wrong programming the MMU. The ESR_EL1 reports that it is a Permission fault, level 2. Here's what I'm trying to accomplish: 4GiB space, 4kiB...
  • ARMv8 EL1 MMU
    Hi,     I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1. I am not able to set sctlr_el1.M bit when ever i try to set this bit the...
  • TTBR1 translation fault when using an identity mapping
    Hello everyone, I'm experimenting a bit with MMU after understanding its core principles. Specifically I can successfully enable it with an identity mapping for TTBR0 (no TTBR1) on a Raspberry Pi 3...
  • Different between AF vs AP (MMU Setup)
    What is different between AF & AP? I understand AP = permission access as read/write/readonly/no access but what is AF?
  • Trouble configuring MMU for 2MB block mapping
    So I'm working with QEMU and AArch64 mode and using the MMU. I've succesfully mapped 4K blocks, but I'm having trouble mapping 2M blocks. My configuration is such that the L1 entries are 1GB blocks, L2...