• Non-Cacheable memory and DMA on armv7a
    Hi ! Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0). We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro...
  • ARM Cortex-A9 | Non-cacheable memory range
    Note: This was originally posted on 23rd May 2013 at http://forums.arm.com Hi all, I am designing an application on xilinx zynq 702 board which comes with two(core) arm cortex a9 processors. I am using...
  • shareability attribute for armv8 cortex a-53
    Hi, I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512. My question is how...
  • CPUACTLR_EL1 and S3_1_C15_C2_0 in Cortex-A57 TRM
    hi, experts:  In Cortex-A57 TRM chapter 4.3.66 : It defines CPUACTLR_EL1 register, but this register name is not CPUACTLR_EL1. Its name is S3_1_C15_C2_0. Why? best wishes, hi
  • Regarding mismatched memory attributes and cacheability
    As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ My question...