• Cortex A15 SCU
    Hi, I find no introduction about SCU registers of A15 in the TRM. So, can software control SCU? Especially is SCU needed to be enabled by software? Thanks&Regards.
  • Exception / Interrupt for Cortex-A15
    Hi, I would like to know whether my understanding is right or not regarding to the interrupt (exception). When an interrupt is issued, the interrupt is executed at once without the completeion of the...
  • ARM cortex A15 hardware simulatenous multihreading.
    Dear All, Does ARM cortex A-15 support some kind of Hardware multithreading? how can I disable it? Thank you so much.
  • how to enable am335x Monitor debug-mode
    Hi , The monitor debug mode can be configured in DSCR, which is writable via APB interface for am335x. But,  I read the DRAR(MRC p14, 0, <Rd>, c1, c0, 0) and DSAR(MRC p14, 0, <Rd>, c2, c0, 0). Both of...
  • Cortex-A8/A15 L1 cache
    Hi, I would like to know whether the cortex-A8/A15 L1cache has ECC or parity check for error checking, or not. I know L2 cache has ECC function. Bur I don't know about L1 cache. Please let me know. Best...