• Cortex A53 : Cache policy setting
    Hi, Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? I'm enabling the caching using the SCTRL register...
  • unaligned data fetch in Cortexa9
    I have a question related to data fetch, when on gdb debugger I do an address read say as: X 0x81000000 Then it will fetch 64 bits as you told in reference to Cortex A9 If further I do X 0x81000004 Will...
  • How get ARMv7 cache size
    Hi everybody!! I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15). In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the...
  • shareable domain and cache policy problem
    Hi, I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE...
  • Cortex-A9: Eviction of dirty line from the region marked as Only "Inner Cacheable" from L1 cache - will if be allocated into L2?
    Hello, Consider following scenario: A 4 KB page starting @0x80000000 is marked as Normal Memory, Inner Cacheable, write-back, non-shareable, non-outer cacheable, L2 is inclusive cache. Now, the s/w writes...