• Which ARMv8 register controls cache partitioning
    Hi ARM folks, Which register controls the cache partitioning behavior on ARMv8 chips? My group is working with a Cavium ThunderX, and we're trying to experiment with different cache partitioning...
  • Can Cortex-A53 l2 cache be controlled seperatly?
    Hi Experts, I'm researching Cortex-A53 cache. Can Cortex-a53 l2cache be enable/disable independently? Is it possible to only enable l1 cache and disable l2cache? Does cortex-a53 support l2cache...
  • About PL310 cache controller and data aborts
    Hello All, I am working on a automotive product based on i.MX6q and recently facing an issue where we see kernel error with message "imprecise external abort". I am trying to analyze it and need to know...
  • How to access the system control register?
    Hi all, I am trying to access the system control register in my ARM C program. The code (with heading 64 bit) I used is presented below. However I got the following error message during compilation. ...
  • Cortex A-35 cache L2 content access
    Hi, I'm currently working on an SCO (i.MX8QXP from NXP) containing an A-35 cluster (4 cores) with a L2 cache. Is there anyway to access the content of the L2 cache? Our current debugger, Trace32,...