• How get ARMv7 cache size
    Hi everybody!! I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15). In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the...
  • Exploring How Cache Coherency Accelerates Heterogeneous Compute
    Cache Coherency and Shared Virtual Memory The Heterogeneous System Architecture (HSA) Foundation is a not-for profit consortium for SoC IP vendors, OEMs, academia, SoC vendors, OSVs and ISVs whose...
  • How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size?
    Hello, I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I  the system there will be a cortex A7 master(64bytes cache line). My question is:...
  • Cortex-A7 cache line size
    Hi All, when I read the ARM® Cortex -A Series Programmer’s Guide for ARMv7-A I found that at page 8-12 Tabel 8-1 Cache features of Cortex-A series processors (continued) there is a field say that...
  • ARM1176JZ-S, cache confg: effective cache size calculation
    Note: This was originally posted on 22nd February 2009 at http://forums.arm.com Hello, 1) I am using ARM1176JZ-S core with WinCE Platform. The cache memory is configured as follows     DCache: 128 sets...