• Use GICv3 legacy support
    I'm using a cortex-a53 FVP model. It comes only with GICv3, but by reading the ICC_SRE_EL3.SRE bit I see this implementation has legacy support. Before leaving EL3 I configure all interrupts to group...
  • GIC-v3: control of group 0 interrupts activation and selection
    Hi, I have two main questions, about the handling of group 0 interrupts: from my understanding of the GIC-v3 documentation, any secure OS (EL1, SCR.NS == 0) has access to ICC_IGRPEN0_EL1: Am I correct...
  • Resetting GIC by SW?
    Hello, we have a board using Armada 3720 SOC, which contains two Cortex-A53s and one Cortex-M3 used as secure-coprocessor. The interrupt controller is GIC-500. The M3 has access to all registers that...
  • AArch64/GICv3:ICC_SGI1R_EL1: AFF1
    I wonder, is AFF1 in ICC_SGI1R_EL1 also a bit-mask or does it address directly the cluster? So does AFF1 == 3 address cluster 3 or cluster 0 and cluster 1.
  • GICv3: setting G1SEN / G1NSEN in GICD_CTLR
    During my experiment with GICv3 using ARM Foundation platform, I tried to set GICD_CTLR value from 0x0 to 0x37 (ARE S/NS + Enable G0, G1S and G1NS) and I got the surprise to see that the finale value...