• Regarding mismatched memory attributes and cacheability
    As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ My question...
  • Cortex-A15 MPCore: How to Enable Monitor Debug Mode
    Hi experts, I want to enable monitor debug mode for Cortex-A15 MPCore. I tried modifying DSCR[15] bit but watchpoint event still won't generate exception/abort. Core was in no-debug mode before modifying...
  • How should I do if I want to enable only one single CPU on a Cortex A9 MPCore(2 CPUs)
    Hi, all When I was porting Minix 3 OS to Zedboard (Zynq 7000 All Programmable SoC) the system always hanged at refresh_tlb. What's strange is that refresh_tlb had been performed at KERNEL booting up,...
  • arm cortex a9 c++ support
    Hello, I'm new to arm cortex a9. how good does the compiler support C++11 or C++14 on bare metal? where can i find the latest compiler? I use Xilinx Zynq 7010 SoC, which comes with a Dual ARM® Cortex...
  • ARM Cortex-A9 MPCore check stack usage
    Hi experts, I want to check the actual usage of my program on Xilinx SDK 2015.4. I connected to ARM Cortex-A9 MPCore#0 using the connect command in XMD console as shown below: When I used stackcheck...