• Cortex-M0+ hangs on return
    During debugging the Cortex-M0+ (ATSAMR21G18) all of a sudden hangs. Stack looks fine. LR contains the correct return address (odd), which based on the BX instruction description ( http://www.keil.com...
  • Random Hardfaults on a cortex-M7 microcontroller
    Hello, I am facing random HardFaults on a cortex-M7 based microcontroller (STM32F722). They happen at various places in code, sometimes even during stack's initialization. Stack's analysis do not...
  • What is the difference of DMB and DSB instruction?
    Dear sirs, From the specification from ARM architecture, DMB needs to make the load and store operation before DMB instruction have an explicit ordering. However, the description of DMB is a loop which...
  • How to debug cause of Hard Fault on CortexM0?
    Dear everyone, I am developing an MCU system by using the DesignStart Pro, CortexM0 version. I program the DesignStart Pro RTL into Altera FPGA, and I use Keil C for software building. The system...
  • dsb and dmb
    Hi all: I have some questions about DMB and DSB in armv8. (1) In armv8 Reference Manual doc, it says " The DMB instruction does not ensure the completion of any of the memory accesses for which...