• Invalid entry - mmu page tables
    Hi, I'm pretty much new to this. I have Level 2 table (for ARMv8 - 64KB granule) with multiple 512MB block entries inside. Some of those blocks are not valid (belong to the reserved/not accessible memory...
  • CPU Reset during a Debug session
    Hi All, I am trying to reset the CPU in the middle of a debugging session. I am using Application Interrupt and Reset control register by setting the SysResetReq bit in the SCB block. (this preserves...
  • Enable and disable MMU page table caching in L2
    Hello, I am using a dual core Cortex A9 CPU and I want to enable MMU caching in L2. By default all the DDR memory region is set as non-cacheable. But then I want only the DDR regions allocated...
  • dump MMU translation table for A9 in Linux
    Hello, I would like to know how to read the translation table info for A9 from embedded Linux. In freeRTOS I have translation_table.S but I do not find anything similar for ARM architecure in linux...
  • Interrupt switching during Late Arrival- CortexM3
    In Cortex-M3 manual, it is mentioned that during Late Arrival, when low-priority interrupt (LP) has already pushed 8 registers to Stack and high-priority interrupt (HP)occurs then, for (HP), we don't...