• ACP and DMA usage on A53
    Hi, I'm using DMA transfering data through ACP on A53. According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each...
  • Why is there an ACP interface for many ARM processors?
    Dear sirs, I read ACE specification and ARM processor documents for ACP explanation. I always have some questions about ACP. As soon as you know, ACP exists in SCU for data coherency. Q1: The document...
  • AXI write outstanding transactions causing problem in image data
    Hi All, I am facing one issue due to AXI write outstanding transactions. Few of vertical lines in my image data has order issue,i.e. pixels are re arranged randomly within line. I was curious why...
  • How to use L2 cache as memory from ACP access on zynq Cortex A9 ?
    Hi, I'm a FPGA designer and this new project is challenging for me because it has to deal with ACP port and L2 Cache of the ARM core of the Zynq FPGA device ! So it's new and I guess will need some...
  • ACE-Lite Master and Slaves
    Hello Ashley,       I have couple of basic doubts w.r.t ACE-Lite Slave.       The AMBA spec for ACE-Lite says that " ACE-Lite is used by master components that do not have hardware coherent caches". But...