PoU (Point of Unification)

Hi all, When reading the ARMv8 reference manual, it mentions a concept of PoU. My understanding is that, if the every CPU core in a cluster has its own L1 cache, and all clusters share an L2 cache...
Cache maintanance operation to PoC

Hi experts, I'm quite confused about cache maintanance operation to PoC on Cortex-A9 (with PL310 L2 cache controller). I'm refererring to the following operations: - DCIMVAC, invalidate data cache by...
What is the difference between IPSR and NVIC_ICSR of Cortex-M?

Hello experts, suddenly I have a question. I cannot understand the functionality between IPSR and NVIC_ICSR[VECTACTIVE]. Are there any difference? Of course, I know IPSR can be accessed by MSR/MRS of...
What's the difference between LDAXR and LDREX

Hi experts: In armv8 specification, I have found two types of exclusive access instructions: LDAXR/STLXR and LDREX/STREX. I have some questions about these instructions: (1) What's the difference...
What's the difference between ETM and Debug?

In the ARM core such as cortex-R4, it has ETM and Debug so I want ask What's the difference between ETM and Debug?