• LDM/STM interruption of Cortex-M7.
    Hi Cortex-M7 specialists. I would like to know the Cortex-M7 behaviors when requested interrupts. In the Cortex-M3 case, LDM/STM and DIV will stop execution by interrupt requests (although those can be...
  • ldm/stm with not aligned 4byte
    Hi experts! I want to use ldr/str or ldm/stm to copy memory not aligned 4bytes. I know their input address should be aligned by 4 bytes. but is there any solution to use ldr/str or ldm/stm though src...
  • Hard Fault in cortex m4
    Hello All, Good Morning! I am working on Cortex m4. I have read following about hard fault , "Bus Fault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and...
  • Endian in Cortex-M4
    Hello to all, I am working on ARM Cortex-M4. Since it has 32-bit address bus, therefore I assumed that each 32-bit instruction will be allocated a physical address location in the Flash. But while reading...
  • stmdb instruction *appears* not to work correctly - Cortex M4 / SAM4L
    I'm struggling to track down a problem here. It appears to be that the stmdb instruction isn't pushing all of the requested registers, and when the corresponding ldmia.w instruction executes, it pops...