• ARMv7-A: Cache maintenance operation by VA, performance
    Hi, according to this talk , cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop...
  • L2 cache with cortex-A8
    Hello, Can I assume that with cortex A8 cache invalidate/flush is used only with L1 ? I have some 2 implementation of this routines, one is called L1 and the other L2C-310. I am just not sure if using...
  • Reordering between multiple loads
    Hello, I have a question if following sequence of instructions involving post-indexed LDRs could be re-ordered on say Cortex A8: To simplify, lets consider, r0 = 0xC, Cache line size 16 Bytes ldr    ...
  • Cortex-A8 Pipelined cache maintenance
    Hi, I am new to the Cortex-A8, I would like to know what is the advantages of using "pipelined cache maintenance operations". "Auxiliary Control Register " has the "Cache maintenance pipeline" bit enabled...
  • On Chip RAM is slow after enabling MMU, and using external ram aborts
    Hello All,        I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU. Issue 1: But what I could notice is code region in external ram is executing faster than internal...