• No segmentation fault with unaligned access
    Hi all, It is a well known fact that performing an aligned vector load with an unaligned memory address should lead to segmentation fault. However, when I do try to run code segment below using the...
  • Loads and Stores for unaligned memory addresses
    Hi, I am trying to write a code using Neon instructions for an iOS app, based on a previous code that has been optimized with SSE instructions for a desktop app. The SSE code has memory alignment...
  • Unaligned memory accesses in ARM V7 core throwing some error....
    typedef struct __attribute__((__packed__)) { uint8_t op_code; uint8_t flags; uint32_t logical_block_addr; uint8_t group_num; uint16_t tx_length; uint8_t control; } SCSI_READ10_t;...
  • Could arm-none-eabi-gcc split a LDRD(64bit load) from an unaligned address into two LDR?
    Hi, experts, When testing codes below on Cortex-M4F. It seems armcc(Keil) handles the unaligned memory access very well and the dword load is compiled into two LDR instructions. But gcc generates one...
  • how to  use PLD  instructions
    Note: This was originally posted on 28th November 2012 at http://forums.arm.com NOW I am learning assemalbe function  "memset"  in android version; follow is some : 0:         PLD         (r3, #64)  ...