• Multicore Platform General Purpose Registers
    Hi, experts Ash Wilding Mark Nicholson , I'm wondering for the multicore ARM architecture, are all CPU cores sharing one set of general purpose registers (X0 - X30) or each CPU core has its separate...
  • How to understand AArch64 register 'Operation' column for 'Direct access to internal memory' in Cortex -A53?
    I'm reading "ARM® Cortex®-A53 MPCore Processor Technical Reference Manual". And, in 6.7 Direct access to internal memory part (P.357), there is a problem to understand what is the meaning of AArch64...
  • How to set the CPU affinity of Secure OS for Juno r1?
    Hi experts, I'm using the Juno r1 board with Linaro OPTEE released normal OS + secure OS. After some tests, I find that every time when the Client Application (CA) calls the function of a Trusted...
  • TZC-400 Region Secure Access Discussion
    Hi experts, I know for the TZC-400 each region has an attribute register which has two bits:  s_wr_en   and s_wr_en for controlling secure access. On the other hand, these control registers could be changed...
  • How to Get the PA instead of IPA from NS OS Kernel Module of an AArch64 device?
    Hi experts, Recently I want to conduct one secure-related scanning in TrustZone for some NS kernel memory. To do this, I need at first reporting the PA of the memory from NS kernel. My idea is developing...