• Enabling MMU crashes ARM Cortex A7
    I am working on smp_prime code of ARM - A9. And a i want to use that code for cortex A7. But after making changes like setting smp bit in ACTLR, Making the memory region device and non coherent- then...
  • Cortex-A35 Counter-timer Physical Count register (CNTPCT_EL0) always reads zero
    Counter-timer Physical Count register CNTPCT_EL0 always reads zero on FVP_Base_Cortex-A35x1. I expect the value of this register to change over time. I set $CNTFRQ_EL0=35000000, and $CNTP_CTL_EL0...
  • Juno MMU setup
    Hi, I was trying to change my MMU setup from 39bit address space to 40bit address space in Juno. Previously I was successfully able to map 39bit address space by setting T0SZ=25 and using L1 level...
  • aarch64 MMU: inconsistency in ARMv8 ARM?
    Hello, I try to reconfigure the MMU of an existing project. I try to do this by building upon an example of ARMv8 ARM. The example is the one in section K7.1.2, fig. K7-11, page 7293. I find the information...
  • How to temporarily disable MMU in EL3?
    I am using Trusted Firmware provided by Linaro on Juno Board R1. Now I want to disable MMU in EL3 and do some custom jobs, and then enable MMU again. As I don't want to disturb other codes in EL3, I guess...