• aarch64 MMU: skipping first/second level tables
    Hi ! on armv7 [1] / aarch32 [2] MMU, when using Long descriptor, when the virtual space described by ttbr0 is small enough (1Gb here), the level 1 translation can be skipped, leaving only two levels...
  • Aarch64 - Armv8-a bitwise cyclic shift operation
    Hi all, I am looking for a ROT64 ASM function able to do ultra fast bitwise cyclic shift ? Eventually using SIMD or NEON function. Any tips or Retex ? thanks best regards
  • Unaligned memory accesses in ARM V7 core throwing some error....
    typedef struct __attribute__((__packed__)) { uint8_t op_code; uint8_t flags; uint32_t logical_block_addr; uint8_t group_num; uint16_t tx_length; uint8_t control; } SCSI_READ10_t;...
  • Rowhammer bug on ARMv8
    Hi Everyone, I have been trying exploiting Rowhammer bug on ARMv8 running linux for a university project. The device is a Quad core Cortex-A72 (ARM v8) 64-bit SoC @ 1.5GHz. First i checked the UCI...
  • Issue compiling ARMv8 assembly
    Hi, I am using "gcc-arm-none-eabi-4_9-2015q1" to compile ARMv8 - A53/A57 code and getting following errors while compiling assembly files - I am giving -march='armv8-a' option. I am not sure how to resolve...