• Problem with wear leveling in RL-FlashFS
    Hello all, I am using Rl ARM Library for file system. It's running on a STM32F4 micro, on a Micron NAND flash chip with 16-bit interface. The file system is formatted with FAT16. I have noticed...
  • "Wear Leveling" strategies in RL FlashFS ?
    Hello, I want to implement the RL FlashFS in my design. Many Flash ICs available ensure only 100.000 write cycles. Based on the idea of a Filesystem the amount of write cycles to a File Allocation...
  • FlashFS - power fail and wear levelling
    Can anyone explain how the FlashFS handles loss of power? I am concerned about losing data that has been buffered but not written during a power failure. I will be writing directly to SPI flash chips...
  • RL-FlashFS Wear Leveling, powerfail safety
    Hi. I'm considering to use the ARM-RL for development on a STM32 Cortex M3 CPU and has been looking at the RL-FlashFS and is wondering if it supports wear leveling and if it is 100% safe concerning...
  • wear are the clases?
    im tryin to see the header with cout in. i looked in keil and c51 and uv3. i can not see it? wear is it?