• Problem with wear leveling in RL-FlashFS
    Hello all, I am using Rl ARM Library for file system. It's running on a STM32F4 micro, on a Micron NAND flash chip with 16-bit interface. The file system is formatted with FAT16. I have noticed...
  • FlashFS - power fail and wear levelling
    Can anyone explain how the FlashFS handles loss of power? I am concerned about losing data that has been buffered but not written during a power failure. I will be writing directly to SPI flash chips...
  • RL-FlashFS Wear Leveling, powerfail safety
    Hi. I'm considering to use the ARM-RL for development on a STM32 Cortex M3 CPU and has been looking at the RL-FlashFS and is wondering if it supports wear leveling and if it is 100% safe concerning...
  • Removing wear-leveling
    Hi, I'm using a nx2lp-Flex USB controller to develop a mass storage USB token. This chip is 8051 based. Cypress provides source code to implement a classical USB key with a Nand Flash memory...
  • Watchdog strategy?
    Am using RTX (CMSIS RTOS V1) on a STM32G081 (Cortex-M0+). Would like to implement watchdog. MCU has an internal - RC clocked - watchdog hardware IWDG. Would like to add a watchdog task, which checks other...