• Problem with wear leveling in RL-FlashFS
    Hello all, I am using Rl ARM Library for file system. It's running on a STM32F4 micro, on a Micron NAND flash chip with 16-bit interface. The file system is formatted with FAT16. I have noticed...
  • "Wear Leveling" strategies in RL FlashFS ?
    Hello, I want to implement the RL FlashFS in my design. Many Flash ICs available ensure only 100.000 write cycles. Based on the idea of a Filesystem the amount of write cycles to a File Allocation...
  • RL-FlashFS Wear Leveling, powerfail safety
    Hi. I'm considering to use the ARM-RL for development on a STM32 Cortex M3 CPU and has been looking at the RL-FlashFS and is wondering if it supports wear leveling and if it is 100% safe concerning...
  • Removing wear-leveling
    Hi, I'm using a nx2lp-Flex USB controller to develop a mass storage USB token. This chip is 8051 based. Cypress provides source code to implement a classical USB key with a Nand Flash memory...
  • FlashFS in battery-buffered ram power fail safe?
    Hello, I configured the FFS to have a drive "R:" in a battery-buffered ram. Can anybody say how a power failthe might effect the FFS while reading or writing or appending to a file? I'm not concerned...