• LPC2148 Strange observation
    Hi all, I have seen that in LPC 2148 for UART0, addresses of register IIR and FCR are same. Why? and how they work then? Please share....
  • CA9MP - Join and Leave coherency
    Note: This was originally posted on 23rd July 2012 at http://forums.arm.com Hi, I have some thoughts regarding joining and disengaging cores to the coherency: In the bootstrap, the case is very easy,...
  • Accelerator Coherency Port
    Note: This was originally posted on 25th January 2013 at http://forums.arm.com Hi all, I'm trying to use the AcceleratorCoherency Port of the ARM A9MPCORE in the Xilinx Zynq platform ( http://www.xilinx...
  • I-cache coherency maintence
    Note: This was originally posted on 14th February 2011 at http://forums.arm.com I'm a newbie in ARM. It's said that in case of multi-core I-cache coherency not maintained by SCU even if memory marked...
  • what is this?
    unsigned char cklf; SPICLK = 0; // Max SPI clock SPI_CTRL = 0x02; // Connect SPI controller to Radio // switch to 16MHz clock: RACSN = 0; SpiReadWrite(RRC | 0x09); cklf = SpiReadWrite...