• AXI ID problem for cascaded interconnect design
    Note: This was originally posted on 18th December 2010 at http://forums.arm.com As we know, the interconnect can add bits  to ID fields to indentify the master issuing the transaction.  In the SoC design...
  • NIC-400 Interconnect generation issue
    Note: This was originally posted on 27th December 2012 at http://forums.arm.com Hi , I am using NIC-400 for AXI 128x64 interconnect. 1-slave X 2-masters. Read transactions with arsize=4,arlen(burst lenth...
  • AXI 3/AXI 4 Exclusive Access
    Note: This was originally posted on 14th June 2011 at http://forums.arm.com Hi, I have a query  regarding Exclusive Access in AXI 3/ AXI 4. The spec does NOT say anything about this behavior, hence I...
  • AXIS AX110xx series Help!
    Has anybody used this line of chips with the Keil support software? I've looked around and it's either Freescale's Coldfire series or ASIX's AX110xx series for an industrial network of control systems...
  • Some questions of AXI
    Note: This was originally posted on 14th November 2011 at http://forums.arm.com >>In AMBA4 AXI rev 2.0, in chapter 4.1 About addressing options: >>Burst must not cross 4KB boundaries to prevent them from...