• Load/Store instruction cycle calculation
    Note: This was originally posted on 23rd February 2010 at http://forums.arm.com Hi,     LDR instruction in cortex-m3 require 2 pipeline cycle means 6 clock cycle. 2-cycle is require for fetch and decode...
  • Hello Per
    Dear Per, Thanks For your Reply. If I have UART 1 code then I never raised this question. And really Your post is very touchy You should register on every forum and paste same answer on post...
  • Problem with load and store data
    Hey all! I'm using Keil-uV3. Chip LPC2214 (Philips Semiconductors) I have an external memory device connected to the expansion board. The external device is using /CS0 and /CS1. Memory bank is 32 bits...
  • Baud & Bits per Second
    If there is 1 bit per baud then baud rate and bits per second are the same ! Of course technology has come a long way since the BEL103 and BEL212 modems came out. The idea is to pack more intelligence...
  • Time spent per task in RTX
    While running a multi-threaded system on coretx-M0+ using RTX, I want to measure percentage of time spent in each task on the CPU and time spent in idle task. Can anyone suggest a way to do that?