• Status flags during bit-level operations
    I can understand that during ANL or ORL operations at bit level, there won't be any change with the status flags of the PSW. However, if a CPL or CLR or SETB operation is performed on one of the...
  • GPIO state during flash/reset
    Hi, I am new to ARM and the KEIl tools so please forgive if Ive missed something basic here. I have inherited a project using a ADUC7026 and am trying to achieve a tidy up of the project, the...
  • interrupt during reset causes cy7c68013a to hang
    I am using the cy7c68013a dev board to test using interrupts. I have based my code on the example given with the dev board. It all works fine as long as there is no signal connected to int0 during reset...
  • Disturbing UART RXNE/IDLE during automatic window update
    This week I needed several days to find a very obscure UART "bug" in STM32F4. The RXNE and IDLE flags sometimes just disappeared (were reset to zero). The missing RXNE then leaded to a missing byte from...
  • PORT6 momentary pulled low during Reset
    Hello, I am running an application where an external reset from a WDT generates a reset on an ST10F168. When the reset occurs, all of PORT6 on the device is momenterally pulled low, then is pulled high...