• memory barrier
    Note: This was originally posted on 18th January 2010 at http://forums.arm.com Hi, On x86/win architecture there is a function called MemoryBarrier that prevents the CPU from re-ordering read/write operations...
  • ARM V7 memory barrier
    Note: This was originally posted on 18th June 2011 at http://forums.arm.com Hello everyone, i have questions about memory barrier which is implemented in Linux for ARM V7 first let's suppose that we are...
  • Memory barriers and ldrexd - race condition?
    Note: This was originally posted on 2nd October 2012 at http://forums.arm.com Hi - Can someone please please PLEASE help me understand something which is still after a LOT of effort trying to understand...
  • Got the problem
    I think I got the problem. UART is recieving 0x00 somehow. I have to fix my transmitting software. Thanks for you help, Eric.
  • Weird interrupt behaviour on Cortex-A8
    Note: This was originally posted on 4th April 2012 at http://forums.arm.com My current configuration is as follows: Cortex A8 with TrustZone enabled. I have both secure and normal world running. Monitor...