This is the first in a series of blogs covering the migration towards ARM technology in the rapidly evolving telecom-infrastructure market.
A lot has been written recently regarding the challenges facing…
Having previously introduced the ARMv8-R architecture, it’s time to look more closely into its new technology and explain some of the benefits it will bring. I’ll try to convey the key concepts simply…
This year’s ARM TechCon conference in Santa Clara sees ARM disclosing details of its next processor architecture; ARMv8-R. This eighth-generation ARM architecture is already established as …
I often receive questions such as “How can I render shadows with OpenGL® ES 2.0 without an available depth texture extension?”; “How can I render a simple text with OpenGL ES 2.0?”; or “Simple text rendering…
This content was initially posted 10 July 2013 on blogs.arm.comWe are pleased to announce the release of VIXL, a dynamic code generation toolkit for ARMv8 that we hope will enable JIT creators to rapidly…
In 2011 I attended the ARM Global Engineering Conference, where I saw a presentation about a new algorithm used in texture compression. I expected it to be about colour space conversions and perceptual…
At the Develop 2012 conference in Brighton I gave a talk about how we achieved some of the effects in our brand new (at the time) demo Timbuktu. As I repeated this presentation at a number of developer…
This document describes an approach for rendering shadows in realtime for mobile devices using OpenGL® ES 2.0 which does not support depth texture unless the OES_depth_texture extension is available.
How to get the most out of the memory interface The choice of DDR memory is a key factor in determining the cost and power of the smartphone. Low cost smartphones typically use a single 32-bit memory…
ARM products in server and networking? Yes, it’s happening and AMBA® 5 CHI is a big part of making that happen. The AMBA 5 CHI protocol enables the latest ARMv8 architecture Cortex®-A50…
ARM® AMBA® 5 CHI Memory Controllers work in concert with AMBA 5 CHI interconnects to provide controls to optimise data flows between many processors and the DDR memory. In this blog I am going to tell…