• ARM Cortex A8 : Enabling D Cache aborts

    Gopu
    Gopu

    I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU.

    I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another external memory region. After the data abort, I could…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is it possible to read the raw L1/L2 cache data and tag bits on the Cortex-A9?

    Alex W
    Alex W

    I've been digging through the Technical Reference Manual (TRM) for the Cortex-A9 and so far it seems that it's possible to gather data about events such as hit and miss rates, but there doesn't seem to be anything on reading the raw data and tag bits…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to do cache invalid on Cortex-A53?

    yan.wy
    yan.wy

    hi,

         I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid.

         Could you give me any suggestion about cache invalid? Thanks!

         The program…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM1136: why the mismatch between cache stalls and cache misses ??

    Zhan Chen
    Zhan Chen

    Something weird when I count both Instruction Cache Miss event and event 0x1 (viz. “Stall because instruction buffer cannot deliver an instruction. This could indicate an Instruction Cache miss or an Instruction MicroTLB miss. This event occurs every…

    • Answered
    • over 5 years ago
    • Processors
    • Classic processors forum
  • ARMv7 performance monitor:how to get L2 cache refill?

    hello_arm
    hello_arm

    The processor is Samsung's Exynos 4210, ARM Cortex-A9, I want to know whether it supports the L2 cache refill or memory access event?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv6 performance monitor: Can I record the instruction which caused the data cache miss

    Zhan Chen
    Zhan Chen

    Hi, I'm new to community.

    I am recently working on cache performance evaluation of a software on arm ( which I did not know much about before) and aiming  to record all the instructions causing a data cache miss.

    Currently, my way is straightforward…

    • Answered
    • over 6 years ago
    • Processors
    • Classic processors forum
  • Guidelines on reducing Cache Miss rate

    techguyz
    techguyz

    Hi Experts,

    Is there any document on general software guidelines in reducing the cache miss rate in the system for ARMV7 architectures ?

    If it is more specific to A/R/M then its great..

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A9: Eviction of dirty line from the region marked as Only "Inner Cacheable" from L1 cache - will if be allocated into L2?

    Hemant
    Hemant

    Hello,

    Consider following scenario:

    1. A 4 KB page starting @0x80000000 is marked as Normal Memory, Inner Cacheable, write-back, non-shareable, non-outer cacheable, L2 is inclusive cache.
    2. Now, the s/w writes to the first word in the page. Let's assume valid…
    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • pc hangs in process of cache setup - Cortex-A7

    Jay Zhao
    Jay Zhao

    In ARM Cortex-A7 platform which includes L1 and L2 level caches,I start cache setup flow as follows:

         1. Enable SMP bit and disable MMU.

         2. Disable I cache in L1, and invalidate it , then enable it.

         3…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Regarding mismatched memory attributes and cacheability

    Hemant
    Hemant

    As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ

    My question is specific to the case when it is only the cacheability…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A8/A15 L1 cache

    Michihiro Yamamoto
    Michihiro Yamamoto

    Hi,

    I would like to know whether the cortex-A8/A15 L1cache has ECC or parity check for error checking, or not.

    I know L2 cache has ECC function. Bur I don't know about L1 cache.

    Please let me know.

    Best regards,

    Michi

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why is the I-cache designed as VIPT, while the D-cache as PIPT?

    Joel
    Joel

    Hi,

    In Cortex-A8's architecture, I'm trying to understand why the I-cache is chosen to be in VIPT form (Virtually Indexed Physically Tagged), while the D-cache is PIPT (Physically Indexed Physically Tagged). I know the advantages and disadvantages of using…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cache maintenance and DMA

    Michael Pulice
    Michael Pulice

    Greetings ARM community,

    I have been tasked with cache maintenance.  The necessity popped up because of DMA issues on USB.

    As a quick (not perm solution) I used the invalidate all routine.  While obviously not nominal in anyway

    it does allow me…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Efficient uasage of PLD instruction in combination with Load instructions?

    josephgopu
    josephgopu

    Hi all,  after a long time I'm back to forum with a question

    I'm posting this question with some pseudo code

    for(i=0;i<100;i++)

    {

    instruction1

    instruction2

    instruction3

    .................

    instructionA : pld [r0]

    ..................

    instructionB :vld1…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Using shareable attribute in MPU configuration of Cortex R4

    Ilan
    Ilan

    Good day all,

    I'm working with a SOC with dual Cortex-R4 that comes with MPU.

    Due to the SRAM limitation and other restrictions, I'm not using any embedded linux or any other SMP RTOS.

    Currently I'm working on the optimization of the flow, so I'm…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Clean Whole Cache on Cortex-A9

    Mark
    Mark

    I am doing some benchmarking and I need to clear the cache before each test. I have this example here:

    Caches and Self-Modifying Code

    However, I just want to clean the whole cache. Is there an easy way to do that? I do not need to know the start and end…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Traffic Mixes in Networking Infrastructure - Base Transceiver Station (BTS) with CCN Interconnects

    Ian Forsyth
    Ian Forsyth

    Introduction

    ARM recently announced the next in the family of CCN (Cache Coherent Network) solutions. Specifically we introduced the CoreLink CCN-508. A quick recap – CoreLink CCN-508 is a cache coherent network providing support for up to 32 fully coherent…

    • over 7 years ago
    • Processors
    • Processors blog
  • Coherent Interconnect Technology Supports Exponential Data Flow Growth

    Ian Forsyth
    Ian Forsyth

    Introduction

    Recently I presented “Coherent Interconnect Technology Supports Exponential Data Flow Growth” at the Linley Processor conference in Santa Clara, CA where I announced a new ARM coherent interconnect product for enterprise applications, the…

    • over 7 years ago
    • Processors
    • Processors blog
  • Page Colouring on ARMv6 (and a bit on ARMv7)

    Jacob Bramley
    Jacob Bramley

    Page colouring is a technique for allocating pages for an MMU such that the pages exist in the cache in a particular order. The technique is sometimes used as an optimization (and is not specific to ARM), but as a result of the cache architecture some…

    • over 7 years ago
    • Processors
    • Processors blog
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