Hello expert:

In MSP2+ board, I found a micro USB connector and some ARM debugger connectors. Can I configure FPGA and run DS-5 using the same micro USB?

Thanks

Jimmy

Hi,

I am using Quartus Prime Lite 17.0.2 for building Cortex-M3 DesignStart RTL.

I can successfully build the RTL, but I got some critical warnings as follows. Can I ignore these warnings? Is there any effects on the design by these warnings?

Critical…

All,

I received the Versatile Express Cortex-M Prototyping System + and am using DesignStart. I powered on the board and the operating system booted up without any problems.

In the V2M_MPS2/MB/HBI0263C/board.txt file, the following are the sequence of…

Hello, I started to tinker with the most basic Cortex-M0 from the DesignStart.
I am using Modelsim Student Edition, which run only on Windows (or Linux through Wine).

I tried to start with Linux to see if at least the "make" commands are working. Problem…

I am currently in Evaluation phase of ARM Design Kits.

I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide to compile the RTL and run the tests.

But, unfortunately after compiling the RTL I am getting a stack…

I am currently in Evaluation phase of ARM Design Kits.

I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide_100895_0000_00_en.pdf

to compile the RTL and run the tests.

But, unfortunately after compiling the…

I download arm cortex m3 prototype  to the CYCLON 5 FPGA .Then use keil to debug the software but when click he debug button ,I encountered an error like the one shown above.

I don't know how to solve the problem 

Hi,

I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

Hello,

I'm trying to connect the DesignStart Eval System to the BME280 Environmental Sensor via SPI. I used the SPI Shield0 Pins (EXP[11 to 14]) to set the connection and activated alternate functions in uVision for these pins. But how can I set up the…

Dear all

I encounter a confusion that  I compile a piece a c code and generate HEX file( as instruction rom's initialization file) which is download to the fpga whit the cortex m3 prototype of Verilog code .but the M3 system can't run itself .when I…

I use the ARM Cortex-M3 DesignStart Eval on the FPGA platform, I use J-link to download the program to the system but the system is not properly implemented. I downloaded the generated Hex file via J-link to the FPGA development board via Keil. Is the…

Hi

I have download the Cortex-M0 DesignStart Eval file (AT510-MN-80001-r2p0-00rel0),
and read the ARM FPGA board (MPS2+) datasheet.

The MPS2+ have many peripheral devices but we don't need it,
so we want made a platform for our use.

The user guide…

Hi,

I am using Cortex-M0 DesignStart Pro. I want to port the Model to FPGA, where I do not need any clock gating or power management. Is there a way to remove the PMU completely?

Best regards,
LeChuck

We are using Cortex-M0 DesignStart Pro to design MCU. When we use SWD to download grogram to flash in FPGA(Cortex_m0 mcu inside),  we cannot to connect keil with FPGA, and Keil shows:" Could not stop Cortex-M device!Please check the JTAG cable. "…

Hi,

I am using the SoC design from Desgn Start - Eval version for Cortex-M0 with only modification of using Xilinx Block ROM as the Memory for FLASH ROM as well as for RAM.

And my goal is to load the application into the FLASH ROM (Xilinx Block ROM) using…

Hi,

I'd like to try and use external BRAM as the I/D memory for the Cortex-M1 DesignStart package for Xilinx FPGAs. The reference examples for Arty boards use the internal TCMs.

I've built a design in Vivado with a BRAM connected to the AXI3 port mapped…

Hi, My name is Vedula. My back ground is 23 yrs in ASIC industry. Did Design/Verification/Validation. I want to get my hands dirty with DesignStart. I am interested in FPGA part. 

I Just downloaded Cortex-M1 DesignStart FPGA - Xilinx Pkg.

To start with…

Hi,

I want to simulate CM3 Designstart with Modelsim.

When I launch Modelsim from Quartus 17.2 most of the files compile. But I get the following error:

** Error: C:/projects/AT421-MN-80001-r0p0-02rel0/smm/logical/smm_common_fpga/verilog/fpga_pll_speed…

Hello together, I am little bit confused regarding to the Cortex-M0DS comparability to Altera FPGAs.

On one hand, according to the information out of the white paper An introduction to ARM Cortex-M0 Design Start it must be possible to run the Cortex-M0…

Such as the title, I have a board of MPS3

I want to try to use the microphone to input the sound, then output through the speaker.

But I have been unable to find a way. I hope someone can point me out. Thank you.

Hi,

I want to buy above said board. But is based on Altera. I am not familiar with Altera. I am familiar with xilinx. Is there a similar board with Xilinx?

Thank you.

Regards,

Vedula.

Hi. First of all, thanks for your attention in advance. I have to say that I am completely new in FPGA programming, but I could have never imagined that running an example with a documentation explaining it step by step could be so cumbersome and error…

Hi.

I started to play with DesignStart FPGA and implemented example design to a Xilinx Arty board. I successfully imported BSP to Keil, did some changes there and generated a new bitstream. Now I would like to start debug session in Keil, but I don't have…

Hello all,

I downloaded the Cortex-M1 DesignStart package for Xilinx FPGAs and followed the instructions given in the training videos. However, the HDL wrapper for the block diagram appears under "non-module files" in Vivado. Due to this I am not able…