Hi,

I am using Quartus Prime Lite 17.0.2 for building Cortex-M3 DesignStart RTL.

I can successfully build the RTL, but I got some critical warnings as follows. Can I ignore these warnings? Is there any effects on the design by these warnings?

Critical…

All,

I received the Versatile Express Cortex-M Prototyping System + and am using DesignStart. I powered on the board and the operating system booted up without any problems.

In the V2M_MPS2/MB/HBI0263C/board.txt file, the following are the sequence of…

Hello, I started to tinker with the most basic Cortex-M0 from the DesignStart.
I am using Modelsim Student Edition, which run only on Windows (or Linux through Wine).

I tried to start with Linux to see if at least the "make" commands are working. Problem…

Hello,

For my bachelor thesis I have to implement the RTL-Code of the Cortex-M3 in the DE-10 Standard Board.
The FPGA on the Terasic DE-10 Standard is the Cyclone V  5CSXFC6D6F31C6.

If I try to compile the ".sof" file of the Eval package in Quartus Prime…

Hello,

I try to implement the Cortex-M3 processor on an FPGA via Quartus Prime. I set up the SSE050 Subsystem and tried to connect several peripherals to the board. I want to test the functionality with a uVision project lighting some LEDs. To have access…

I download arm cortex m3 prototype  to the CYCLON 5 FPGA .Then use keil to debug the software but when click he debug button ,I encountered an error like the one shown above.

I don't know how to solve the problem 

。。。

Hi,guys.

We have already  applied for Cortex-M3 DesignStart Pro and purchased the V2M-MPS2+ motherboards.

To my knowledge, V2M-MPS2+ motherboards was designed for DesighStart Eval and can be integrated with arm Embed OS easily.

So, my question is:

1, can…

hi, GUys

   i buy a mps+2 board  and try to implement  mbed_blinky examples. but i meet issues on debugger and download axf files.

     now i can:

        1. export mbed_blinky examples for keil 

        2. compile success and generate axf file

        3. download fail

Hi,

I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

Hi,

I am using the MPS2+ board to debug my DesignStart Cortex-M0. The core is up and running and now I want to program the onboard SRAM. On the SDCard I can see that \MB\HBIO263C\AN387\images.txt expects an axf file.

Is it possible to generate an .axf…

Dear all

I encounter a confusion that  I compile a piece a c code and generate HEX file( as instruction rom's initialization file) which is download to the fpga whit the cortex m3 prototype of Verilog code .but the M3 system can't run itself .when I…

I am new to design start. I have just received the MPS2 board. We have a multi core SOC design and I wanted to know hoe to  program the individual cores via .axf files.

Hi,

II refer to the example MCU system level in the document "arm_cortex_m0_designstart_eval_user_guide", put it into MPS2+ after synthesis, the software uses the following example in this directory.

D:\CMPS3\AT510-MN-80001-r2p0-00rel0\systems…

Hi,

my question sounds trivial, but I just cannot find the register for the program counter in my Cortex-M0. According to the Register TRM it should be R15, which is not available in the GPR module.

Best regards,
LeChuck

//edit: talking about the Verilog…

Hi,

I am working on a GPIO IP for Designstart Pro Cortex-M0. Now in my Simulation there are some Read-Modify-Write cycles in order to set only single bits in a 32 bit register.

If the GPIO register is 0x0000000X and I just want to set bit 16, GCC produces…

I use the ARM Cortex-M3 DesignStart Eval on the FPGA platform, I use J-link to download the program to the system but the system is not properly implemented. I downloaded the generated Hex file via J-link to the FPGA development board via Keil. Is the…

Hi

I have download the Cortex-M0 DesignStart Eval file (AT510-MN-80001-r2p0-00rel0),
and read the ARM FPGA board (MPS2+) datasheet.

The MPS2+ have many peripheral devices but we don't need it,
so we want made a platform for our use.

The user guide…

Hi,

I am using Cortex-M0 DesignStart Pro. I want to port the Model to FPGA, where I do not need any clock gating or power management. Is there a way to remove the PMU completely?

Best regards,
LeChuck

Hi,

     I am using Cortex-M0 DesignStart Pro. When I simulation intrrupt_demo test case, I found that IRQ[31:0]  always 0, Is this correct?

     I saw the document , the interrupt_demo is Demonstration of interrupt features, but if no interrupt signal input…

Deare

       I am using Cortex-M0 DesignStart Pro. When I use my program to simulation, I found the HADDR from 0, to 4, and the to ffff_fffd8, the  HRDATA is  0x2000_06f8 and 0x800_0159，the HADDR should not be ffff_ffd8，So I think it's unusual, but I don't know…

We are using Cortex-M0 DesignStart Pro to design MCU. When we use SWD to download grogram to flash in FPGA(Cortex_m0 mcu inside),  we cannot to connect keil with FPGA, and Keil shows:" Could not stop Cortex-M device!Please check the JTAG cable. "…

Hi there,

Why the address of reset handler is different from waveform and assembly code for hello testcase?

This is obtained after compiling hello.c using Keil uVision 5.

Reset_Handler
0x000001c0: 4809 .H LDR r0,[pc,#36] ; [0x1e8] = 0x2a1
0x000001c2:…

Hi,

I am using the SoC design from Desgn Start - Eval version for Cortex-M0 with only modification of using Xilinx Block ROM as the Memory for FLASH ROM as well as for RAM.

And my goal is to load the application into the FLASH ROM (Xilinx Block ROM) using…

Hi everyone,

                   I am Aman. I am new to the ARM cortex m. As per specs, I tried to download GNU MAKE-3.80 and Binutils-2.22. But I didn't get much. Can anyone help me, that from where I need to downloads both tools and how to installing and set…