Hi All,

Im new to the Arm Community and Arm processors (newbie), and my question is as follows: Atmel ATSAMD20e  implements ARM cortex M0+ processor based on ARMv6 architecture. It allows upto 32 external interrupts, with the interrupt signals connected…

Hello everyone,

I have an LPC4337 running uCLinux. I'm trying to get code to run in the M0 in parallell.

I load the code to 0x10080000, set the M0APPMEMMAP to 0x10080000, release the M0APP Reset and nothing happens. I have to reset the M0-core using…

We are using ARM CM0+ in our embedded SoC design and I noticed that boot takes a long time. Specifically, I saw that it took ~18K cycles after the unreset before we executed an instruction that I recognize (which is inside __rt_entry). We are of course…

Dear Guys,

    In typical SoC product, the FLASH memory is initially empty after being shipped from factory, in which the data are all "0xFFFF_FFFF".

    I am curious how Cortex-M0 deals with the undefined instruction data "0xFFFF_FFFF…

I have initialized stacks for various tasks with content as expected on SVC interrupts.  I'm not able to dispatch an initial task via the "normal" dispatch function.  On this first dispatch, the processor is not in an exception handler, but the LR is…

hi, as i posted before I'm trying to integrate an adder to my architecture however no body replied

so please if anyone succeeded in implementing a hardware design on his FPGA, and of course when i say a hardware design it doesn't include the predefined…

Hello.

I'm studying about the tail chaining of Cortex-M0.

Is it same as Cortex-M3 or M4?

Best regards.

hi

I'm using the soft-core Cortex-M0,keil uvision 5,vivado 14.4

I am trying to implement a filter on my Cortex m-0 based FPGA

the main idea of this project is to create an accelerator from my C code to reduce the execution time ..and since my accelerator…

Hello, Everybody. I have several questions.

1. Please See the NVIC_Type structure. I don't understand about why ISER,ICER,ISPR and ICPR use size of array 1( I think It can use just __IO uint32_t ISER; ), and what does RESERVEDs do???

2. I would like…

What is the use or application of SV Call and NMI Exception in ARM Cortex M0 .

Is it someway related to RTOS?, if so , how?

Hi,

As I have found in:

Cortex-M0+ Devices Generic User Guide: 2.1.3. Core registers

There is information about instruction behaviour during interrupts:

The interruptible-restartable instructions are LDM, STM,…

I could not clearly understand the alignment issues present in ARM. Sometimes I get BUS ERROR while running an assembly file but don't know how to resolve it. Some of the doubts:

1. Is it better to store registers pairwise or individually on the stack…

I need to be able to handle long bitfields as effectively as possible. Right now I need up to 64 bits in length.

Are there instructions to set, clear and test individual bits in one cycle available for some of the architectures? Which? Particularly, will…

Hi, I wanted to write a simple program that doesn’t use interrupts or check any of the possible error flags, but that shows a simple UART application for receiving data. This is a part of the code I wrote.

int uart0Getch(void)

{

  if (LPC_UART->LSR…

Hi,

I have two M0 projects.  The first project has only one assembly file startup.s.  The second project has one assembly file and one C file.  When I checked the memory map file of the second project (shown below), there are some extra object codes included…

How do I decide which ARM board to go for if I am aiming to use it as a micro-controller to run sensors, actuators, motors, and solar panels? And I wish to power up the board via Li-ion battery pack.

I need some indications to begin writing a program.

Write a compare routine to compare 64-bits values , using only two instructions.

Thanks for your indications !

Hi,

I'm somewhat confused with the Thumb mode code size.  My understanding is compiling with ARM mode will generate 32-bit instructions and compiling with Thumb mode will generate 16-bit instructions.  When I compile my Cortex-M0+ project (which should…

I write the code as following to evaluate the expression n = n / 2

asrs r0, r0, #1

But, I found the GCC will translate the expression n = n / 2 into the following instruction

lsrs r1, r0, #31                                                                             

adds r0, r1, r0

asrs r0, r0, #1

Why does it need to add the…

Hello all,

I am confusing by SysTick interrupt behavior.

Even if SysTick clock was processor clock, the processor woke up from Sleep or DeepSleep mode by SysTick interrupt.

My understanding is that the processor clock will stop during WFI execution (i.e…

Hello everyone,

I'm using a MKL05Z32 of Freescale that has a Cortex-M0+. I would like to know the priorit of the Systick timer available to use.

Thanks.

Frederico

Hi,

I needed to know where i could get arm cortex m3 soft core. Its for my masters thesis for which i'll be also using Keil uvision 5.

Thanks in advance

Can someone tell me how many extra gates the 1-cycle multiply uses? If there was a 64-bit result, how many more gates would be used? Can these gates also be used to find the reciprocal of a number so instead of divides, the coder multiplies the reciprocal…