Hi Experts,

A8 is meant for single core and A9 is for multi-core based.

Consider in case of SoC is build with single core of A9 and A8 how we could compare both in terms of some metrics/parameters like power/speed ?

Hi, arm experts,

We want to use ARCH32 mode in secure EL1, I see some descriptions in ARMv8 Arch Reference Manual about Secure EL1 ARCH32 mode as follows:

One is the VBAR(secure), it is mapped to  VBAR_EL3, the other is SCTLR (secure), it is mapped to …

would u mind telling me please I'm really interested in this kind of stuffs.

Hello everybody,

Section 18.8 Exclusive access of Cortex-A Series Programmer's Guide says the following:

STREX can be considered as a conditional store. The store is performed only if the physical address is still marked as exclusive access (this means…

When using gcc to compile c code for ARM platform, we set object platform by using:

     -mcpu = xxxxxx

To what extent will that affect results of compiling ?

For example:

     -mcpu = cortex-a8

and

     -mcpu = cortex…

I read TZ whitepaper. TZ's software architecture includes normal OS, secure OS, and a monitor that manages switching between two OS. The notion is clear. But how to implement them confuses me.

Running and managing two kernels on a SoC needs mechanism…

Below is from ARMv7 Architecture doc.

          An exception is described as asynchronous if either of the following applies:
          — the exception is not generated as a result of direct execution or attempted…

Dear all,

I am interested in a scenario where I want to host two guest OSes above a bare-metal hypervisor on an ARM mobile platform. The total available memory platform is 4GB where I want to expose exclusively 2 GB of continuous RAM to each guest OS.…

Why are there different encodings of instructions?

What's the idea/background/etc for their co-existence?

Can different encodings be mixed in the code? (Not ARM encodings with Thumb encodings- without ARM/Thumb mode change,

but, like A1 and A2 or T1…

Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message between the 2 cores, I followed the Xilinx example…

what are the minimum hardware requirements to setup wifi on arm-7 processors.

What does it mean that an instruction is a hint instruction, like NOP, YIELD and WFE?

I haven't found any explanations in ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, Issue C.

[EDIT]

Aha, this has already been answered in:

Are…

What can be accessed by MRS/MSR in user mode?

In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1):

Hi

my situation: Running an OS in normal-world which due to an (user) error enters safe state with interrupts disabled. The Hypervisor enters by an FIQ (watchdog) and should reset the normal-world.

No the problem: If the normal-world error happens in an…

Hello All,

I am working on a automotive product based on i.MX6q and recently facing an issue where we see kernel error with message "imprecise external abort". I am trying to analyze it and need to know a few things (which are not very clear in the TRM…

Any idea about instructions marked as UNPREDICTABLE: can it then be UNDEFINED?

In other words: UNDEFINED REQUIRES the instruction to cause UND-exception, but

MAY UNPREDICTABLE do that, or does it have to execute normally except that the result may be…

I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found

an answer to in ARMv7-A/R ARM Issue C.

How is this special?

In the ARMv7-A/R ARM Issue C I found two instructions with odd encoding: PUSH and POP, encoding A2.

What's the Rt's role? I guess Rt and 'registers'-bitlist needs to match?

Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7

PUSH<c> <registers>…

For ARMv7 -A/R systems, the MMU uses an ASID to distinguish between memory pages which have the same virtual address, but which are used by an individual task ( I.e. A task which uses non-Global memory). The ASID is an eight-bit value, from 0-255, assigned…

When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.

But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......

And, if…

Hi, all

What is the content of Context ID Register of ARM Cortex A9. Is it OS that is responsible for assigning the value

of Process ID and ASID? As far as I know, it is so in Linux. Is that the same in the other OSes?

Is it essential to deal with ASID if…

Is there a reason why banked registers SP and LR can't be accessed as r13_<mode> or r14_<mode>, but

one has to use SP_<mode> or LR_<mode> instead? It makes macros and inline assembly difficult.

In document (ARMv7-A/R ARM Issue…

Hi Experts,

I'm reading white paper for ARMv7 and ARMv8.

but when i reading cache part and memory re-ordering, i have silly questions.....

Suppose there are below instructions..

Core A:

     STR R0, [Msg]

     STR R1, [Something…

Hello Community,

I am currently learning hypervisor design using ARM's virtualization extensions (on both ARMv7 and ARMv8).

A note in the ARMv8-A reference manual (section D1.5) mentions:

"In some systems, a Guest OS is unaware that it is running on…

Is it

MOVS pc, r14

or

SUBS pc, r14, #4

This is written in the ARMDEN0013D. but in the table it says next instruction whereas the SUBS pc, r14, #4 means the instruction which was interrupted.