• Is there relation between the de-assertion of BVALID and BREADY signals ?

    Amit Mishra
    Amit Mishra

    Hi,

    I am aware that like other channels, the handshaking signals of the Write Response can assert in any order (that means BVALID and BREADY can assert either together at the same clock edge of one after the other in both the orders). But is there any…

    • over 1 year ago
    • System
    • SoC Design forum
  • Looking for pin/bit accurate AXI4 SystemC models

    Vijayvithal
    Vijayvithal

    Hi,

    I am creating a systemC model for a peripheral which has an AXI4 interface.

    Is there a bit and pin accurate AXI4 SystemC model similar to the ones available for OCP?

    Is it available from ARM, a ThirdParty vendor, or the opensource community?

    • over 1 year ago
    • System
    • SoC Design forum
  • AXI4 Burst Transactions

    surajrgupta
    surajrgupta

    I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.

    Eg. Burst length- Two , Burst size 16 bytes.

    Please give me answers for different types of data bus width say for bus width …

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • AXI Burst Size meaning

    hayk
    hayk

    Dear Community,

    I am reading AXI speck from the ARM, please help better understand the AXI, by answering my questions regarding to Burst transaction.

    a)
    I cannot clearly understand the meaning of Burst size signals - ARSIZE and AWSIZE.
    When there are Bust…

    • over 2 years ago
    • System
    • SoC Design forum
  • AXI ARID AWID

    Vasu
    Vasu

    What is the size of AWID and ARIDs? On what basis size is determined? How the AxIDs are generated?

    • over 2 years ago
    • System
    • SoC Design forum
  • unaligned address in AXI protocol

    dorababu
    dorababu

     i am sending data "NEWDATAA"  which is 8 bytes. and  starting address is 5, which is unaligned address then whether my data is loss or not . please explain how the whole transfer will happens. how the strobe will works. is my data start with aligned…

    • over 2 years ago
    • System
    • SoC Design forum
  • AXI read reordering depth and read interleaving depth. Are they same?AXI

    rssortur
    rssortur

    Is interleave and reorder the same concept?

    My interpretation is a slave can reorder without interleaving, which means entire read burst are reordered with no interleaving. So my understanding is they are different. Confirm my understanding.

    • over 2 years ago
    • System
    • SoC Design forum
  • Why do AMBA AXI does not support AxBURST of decrementing address type?

    rssortur
    rssortur

    Use case which come to my mind is.

    1. Display controller might need to flip an image 180 degrees. Here memory reading pattern is reversed.

    2. Where ever there is LIFO (Last In Fist Out) implementations.

    • over 2 years ago
    • System
    • SoC Design forum
  • AXI transfer

    isounder
    isounder

    Consider Data interface is 64 bit.
    It is Write transfer.
    AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios.

    Scenario 1:
    Burst -> Address:0, size:3, length:1, burst_type…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
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