Hi,
When i power on a ARM cortex A57, How many of the 4 Exception levels will be supported?
How can i set such that only exception levels EL0 and EL1 are supported in my program? How can i activate each exception levels?
I have to set it such that normally…
I'm an arduino guy looking for more power and I'd like to start using the high performance ARM chips such as the A57 and soon the A75, but I'm having an impossible time finding dev boards for anything other than some older ARM chips (I think the highest…
I'm having a SAMA5D26C with a LPDDR2 EDB1332BDBH-1. The CPU boots successfully ROMBOOT and is able to load at91bootstrap from QSPI memory. I get debug output from at91bootstrap, but I fail to load linux.
Investigating this further show me that the…
Hello,
In Cortex, A9 CPU register CPSR tells the current execution mode , bit M[3;0]
I am looking for if there is similar register present in A64 architecture .
Reading ESR_EL3/EL2/EL1, I think this is difficult to determine, if system in IRQ mode or…
Hello!
I'm using a Zybo board with a dual-core ARM Cortex-A9 processor and I'm trying to read (and then write) the registers of the processor. How can I read these values into variables in C code?
Thank you!
Hello,
I am developing embedded software on Zynq MPSOC Cortex-A53 (Armv7/Armv8) for image processing, and I need some help for developing a specific algorithm.
The algorithm involves many calculations of FFT and matrix using. As highest priority, we…
Hello ,
We are working on TI chip which holds A15 as one of the main core in the HW . We are looking for some technical support on A15 .
I appreciate someone from technical team could reach and help me out on that at the earliest .
I will share further…
Hi,
I am working on a hardware platform having 2 Cortex-A15 cores (with virtualization extensions). For routing IRQ's at PL2 to PL3 ( to hypervisor mode), I am setting HCR.IMO bit and it is working fine for core-0. If I set the HCR.IMO for core-1, will…
Hi all,
I have two A15 CPUs and 1GByte of DRAM memory. I want to dedicate 0.5GByte of memory to each CPU. Would the following system work?
(A15) (A15)
| |
----CCI----…
In A7 platform with TZ extension , I know that there is a virtual MMU for non secure world, and I think it should be enabled after entering non secure world.
But the most confusing thing is that what has to be done with cache-----clean , invalidate or…
This question was asked in the 'How to optimize a system with the latest ARM DynamIQ processors' webinar. You can view all other related questions in this blog post.
Hello everyone. I'm trying to understand how to create and make work two separate baremetal programms on two cores of cortex-a9. I'm using Cyclone V SoC. DS-5, arm compiller 5, DE1-SoC board by terasic. I already understand how to work with main core…
I would like to get some confirmation that if we replace A53/A72 with A7/A9 while the SoC architecture is still based on ARM v8 bus & IPs (e.g. CCI400, NIC400, TZC400, GIC500, BP141), does such design feasible and workable?
I need a little digital io for my project since cortex-m is not economical for me I need to know can i use Cortex-a to do some embedded jobs?
