Hi,
In AMBA AHB:-
For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response.
q) For two clock cycle ERROR response, is it mandatory of hgrant must be low after 1st clock…
What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles.
Thanks
I am a Digital Verification Design Engineer.
Currently, I am in the process of developing an UVM Test Bench for AHB 2.0.
I have following questions.
1) From AHB Master side, Can BUSY cycles be inserted in middle of INCR16 burst?
2) From AHB Master side,…
Can i observe the 1KB data that it is written over the STM AXI interface from STM ATB BUS ?
what i mean is that i want to send a 1KB data from STM AXI and observe it from the STM ATB with MIPI STPv2 format.
Hi,
I was trying to understand the state machine of an APB. I was curious on how the PREADY signal is triggered low so that it can exit from the ACCESS state?
If anyone could help me with this basic question, it'll be of great help thank you. :)…
How is it possible for AMBA bus protocol to communicate between ASB bus and APB bus,if they operate in different frequency's? ASB is high performance high frequency bus and APB is low performance low frequency bus..how that communication is happening…
Hi,
Can you please help me in writing assertions to take care on multiple transfer in APB bus?
Thanks,
Rakesh
Hi,
I am working on AXI bus for my college project. For my work I have to add something new in existing architecture. Can someone provide me idea for my work?
I would like to get some confirmation that if we replace A53/A72 with A7/A9 while the SoC architecture is still based on ARM v8 bus & IPs (e.g. CCI400, NIC400, TZC400, GIC500, BP141), does such design feasible and workable?
